1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and its manufacturing process. In particular, the present invention relates to a structure in which particles with nano-scale consisting of at least one type of single-element substance or its compound are densely distributed in an insulating matrix. Further, the present invention relates to a nonvolatile semiconductor memory device having a charge retention layer with excellent retention characteristic by optimizing the work function or the electron affinity between the nano-particles and the insulating matrix, and by optimizing the distances between surfaces of adjacent nano-particles, and its manufacturing process realizing low cost and good reproducibility.
2. Discussion of Background
Heretofore, as a recording medium in which a large amount of data can be memorized and rewritten, a memory device employing a semiconductor such as DRAM or SRAM, or a rotating-disk type recording medium such as a hard disk, an optical magnetic disk or an optical disk, have been present, and systems employing these media have been developed and used. Among these, DRAMs having such characteristics that data-reading and writing speed is high or that high-density integration can be easily achieved, are widely employed as main memory devices for e.g. personal computers. However, since DRAMs have volatility of data (a record retained in a DRAM disappears when electric power supplied from the outside is stopped), which is fatal to a memory device, electric power supplied from the outside is essential to maintain the record and power consumption thereby increases. This characteristic of data volatility is extremely inconvenient particularly when a mobile information device relying on e.g. a battery for power source is used.
On the other hand, a recording medium such as a hard disk system does not have volatility of data. However, it has disadvantages such that the writing and reading speeds are slow and the power consumption is relatively large. Further, from its device structure, there is a disadvantage that it is weak to mechanical vibration and impact. These disadvantages make the hard disk system extremely inconvenient to be used for mobile information devices.
Recent expansion of mobile information devices market for ubiquitous society demands that memory media obtain characteristics of non-volatility, high memory density, high speed performance, realizing good handling capability such as stable operation even under mechanical vibration or impact at a time of mobile use, requiring low power consumption and availability at low cost.
AS a medium satisfying the above-mentioned characteristic requirements, a nonvolatile semiconductor memory device such as a flash memory, a FeRAM (Ferroelectric Random Access Memory), an MRAM (Magnetic Random Access Memory) or a PRAM (Phase-change Random Access Memory) has been expected, and these are currently under development or partially in a stage of practical use.
Each of these nonvolatile memories has advantages and disadvantages. For example, an MRAM has many advantages such as high speed writing and excellent endurance characteristic, whereby it is regarded as the most major candidate for the memory leading the next huge memory market. However, an MRAM is mentioned to have problems such that miniaturization of the cell size is difficult, one of the reasons is that scaling down of MTJ (Magnet Tunnel Junction) element in the MRAM cell causes increase in current for reverse of magnetization of free layer in the MTJ due to increase in coercivity of the ferromagnetic material as the free layer. Besides, the MRAM has some disadvantages in terms of manufacturing cost, and a ferromagnetic material having many process-related technical problems needs to be introduced.
On the other hand, a flash memory has advantages such that since its memory cell is basically constituted by a single transistor only, its construction is simple and the cell size can be made smaller, whereby a highly integrated memory can be manufactured with relatively low cost by employing conventional DRAM process techniques. From these reasons, flash memories have already formed a large market as memories for mobile information devices. In recent years, realization of high speed operation and high density integration of semiconductor device have been in progress. Along this trend, researches to achieve high performance such as miniaturization of memory cells, high speed operation and improvement of charge retention characteristic are popularly pursued in the field of flash memory.
In a flash memory currently already widely circulated in the market, for an example of NOR type flash memory, read-out operation of data reserved in an assigned memory cell is performed at high speed within a relatively short time of about 100 ns (nano seconds) or shorter.
On the other hand, data-writing is performed by injecting channel-hot electrons (CHE) from a channel to a floating gate, and data-erasing is performed by discharging charge by Fowler-Nordheim (FN) tunnel current from the floating gate to a substrate or to a source region. In the case of CHE injecting, although moving speed of charge is high, charge-injection efficiency (proportion of CHE injecting current to CHE generating current) is low, and in the case of discharging charge by FN tunnel current, moving speed of charge is low. Therefore, re-writing operation takes long time in both of these methods.
Specifically, it takes a relatively long time such as a rank of 1 μs (micro seconds) for writing and from several hundreds of milliseconds to several seconds for erasing. Therefore, although achieving large volume or low cost is relatively easy in the case of flash memory, its application is limited and the replacement of high speed memories such as DRAMs by flash memories is currently difficult.
In order to reduce the re-writing time to overcome this disadvantage, a method of reducing the physical thickness of a tunnel insulating film preventing the reduction of re-writing time, is considered for example. However, if the thickness of the oxide film is reduced, since extremely strong electric field inversely proportional to the film thickness is applied to the tunnel insulating film when the floating gate is charged, repeated passing of charge through the oxide film by repeated re-writing operation causes a stress, and the oxide film becomes likely to have dielectric breakdown (stress-induced leak current).
When the insulation breakdown occurs at least one point in the tunnel insulating film, most of charge retained in the floating gate leaks and the memory cell loses the data retention capability. Therefore, at present, in order to maintain the reliability of charge-retention, it is necessary to make the tunnel insulating film thick, and it is difficult to reduce the re-writing time. Further, since there is a scaling rule that the thickness of the oxide film and the entire dimension of the cell similarly shrink, the problem of oxide thickness prevents miniaturization of entire device.
Further, it is pointed out that as a result of high dense integration of memory devices, the distance between floating gates of adjacent cells becomes smaller, and mis-readings and mis-writings tends to occur due to strong capacitive coupling formed between them. This influence of the capacitive coupling is particularly remarkable in NAND type flash memories.
From these reasons, the difficulty of miniaturization and high integration of the present bulk-floating gate type flash memory devices will rapidly increase from now on, and it is said that the limit of miniaturization will arise as early as around the year of 2007.
As means to prevent the lowering of charge-retention ability due to insulation breakdown while maintaining the ability of high-speed operation, and reducing the influence of the capacitive coupling between floating gates of adjacent cells, there is a method of retaining charge as it is spatially discreted. As nonvolatile semiconductor memories employing this method, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) memory and a SONOS (the material of gate electrode is a semiconductor instead of metal in MONOS memory. e.g. polysilicon is employed as the electrode material) are mentioned.
As shown in FIG. 4, they are memories having a structure that a tunnel insulating film 2 and a SiNx film as a charge retention layer 3 instead of a floating gate, are stacked, and charge are trapped in the interface states 3a-1 present in the interface and in the trap levels 3a-2 discretely distributed in the SiNx film. Here, in FIG. 4, reference numeral 1 indicates a p-type semiconductor substrate, 4 indicates a gate insulating film, 5 indicates a control gate electrode, 6 indicates a source region and 7 indicates a drain region.
Since the interface state 3a-1 and the trap level 3a-2 retaining charge are spatially discretely distributed, even if a dielectric breakdown occurs at one point in the tunnel insulating film 2, only a local leakage of charge occurs and the charge-retention ability of the memory cell does not drastically change between before and after the occurrence of the dielectric breakdown.
From these reasons, a MONOS memory is superior to a present bulk-floating gate type flash memory in the endurance characteristic, and a MONOS memory is advantageous in terms of miniaturization of memory cells since the physical thickness of the tunnel insulating film can be relatively thinner. However, from reasons such that the depth of the trap level of SiNx film (energy difference between the trap level and the bottom of conduction band for an electron, and energy difference between the trap level and the top of valance band for a hole) is not always sufficient, there is a disadvantage that charge once trapped tends to escape, and absolute charge-retention ability (the charge-retention ability of a cell in a normal state with no dielectric breakdown occurred) is low.
On the other hand, as a method for dealing with the dielectric breakdown of the oxide film and the capacitive coupling problem between adjacent floating gates by retaining charges in a discrete manner as in MONOS memories and for further enhancing the absolute charge retention ability than MONOS memories, a structure wherein the floating gates comprise Si nano-particles and the large number of nano-particles are dispersed in the gate insulating film, has been considered. FIG. 5 shows an example of semiconductor memory device having Si nano-particles. Here, in FIG. 5, the name of each of the constituents in the device are the same as that indicated by corresponding numeric symbols of FIG. 4 except for Si nano-particles 3. The memory having this structure is described, for example, in JP-A-11-186421. The publication describes a structure wherein a large number of Si nano-particles 3 formed by CVD method constitute a floating gate and their periphery is covered with a gate insulating film 4.
In a case where the floating gates are made of intrinsic (containing no impurities) Si nano-particles, an injected electrons are trapped in conduction band states of the Si nano-particles, and the height of potential barrier for the electron is the difference between the bottom level of conduction band of the oxide film surrounding the nano-particles and that of Si nano-particles, namely, the difference between the electron affinities of Si and the oxide film. Since the potential barrier is usually higher than a potential barrier for the traps in a SiNx film in MONOS memories, the trapped electron can hardly to escape to the semiconductor substrate or to the control gate electrode. Namely, the charge retention ability becomes higher than that of MONOS memories.
However, when the charge retaining ability is considered from the viewpoint of potential barrier, the material constituting the nano-particles is preferably a metal rather than Si. FIG. 1(A) is a schematic view showing energy levels in a state that Si nano-particles retain electrons. Here, reference numeral 1 indicates a p-type semiconductor substrate, 2 indicates a tunnel insulating film, 3a1 indicates Si nano-particles, 4 indicates a gate insulating film, 5 indicates a control gate, 9 indicates an electron, 10a and 10b indicate the bottom levels of conduction bands of Si nano-particles and tunnel insulating film respectively, and 12 indicates potential barrier. The injected electron 9 is trapped in the bottom level 10a of conduction band of Si nano-particles. The potential barrier 12 for the electron 9 in this case, is the difference between the bottom level 10b of conduction band of the tunnel insulating film and the bottom state 10a of conduction band of Si nano-particles at the interface between the Si nano-particles 3 and the tunnel insulating film 2, namely, the difference between the electron affinity of the oxide film and the electron affinity of the Si nano-particles. On the other hand, FIG. 1(B) is a schematic view showing an energy level in the case where the nano-particles are made of metal. 11a indicates the Fermi level of the metal nano-particles, and other reference numerals identical to those of FIG. 1(A) indicate the same constituents of FIG. 1(A). In this case, an electron is trapped in the Fermi level 11a of the metal nano-particles, and the height of potential barrier 12 in this case becomes the difference between the bottom level 10b of conduction band of the tunnel insulating film and the Fermi level 11a of the metal nano-particles at the interface between the metal nano-particles and the tunnel insulating film, namely, the difference between the work function of the metal and the electron affinity of the oxide film. Since the work function of many metals are the value larger than the electron affinity of Si, the potential barrier formed by the metal in the oxide film is higher than that in the case of Si. From this reason, it can be explained that metal nano-particles have higher ability of retaining charge than Si nano-particles.